Method of forming a capacitor

ABSTRACT

Methods of forming a capacitor are disclosed. The methods may comprise the steps of forming a substrate assembly and forming a first electrode on the substrate assembly. The first electrode may be formed to include at least one non-smooth surface and may be formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The methods may also comprise the step of forming a dielectric on the first electrode and an uppermost surface of the substrate assembly, and forming a second electrode on the dielectric. The second electrode may be formed to include at least one non-smooth surface. Also, the dielectric and the second electrode may be formed only within the first electrode.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of copending U.S. patentapplication Ser. No. 10/299,752, filed Nov. 19, 2002, which is adivisional of U.S. patent application Ser. No. 09/770,699, filed Jan.26, 2001, and now issued as U.S. Pat. No. 6,960,513, which is adivisional of U.S. patent application Ser. No. 09/286,807, filed Apr. 6,1999 and now issued as U.S. Pat. No. 6,696,718.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is directed generally to a capacitor and methodfor forming a capacitor and, more particularly, to a capacitor andmethod for forming a capacitor having an electrode formed from atransition metal, a conductive metal-oxide, alloys thereof, orcombinations thereof.

2. Description of the Background

Minimum feature sizes in integrated circuits are sufficiently small thatsome fabrication processes are no longer effective. For example, in manyapplications sputter deposition is not effective for filling openings.Furthermore, the smaller dimensions are requiring higher performancefrom components and devices. For example, greater capacitance isrequired from small capacitors. One way to obtain higher capacitance isto use dielectrics having greater dielectric constants. Often, however,it is necessary to heat the dielectric to high temperatures in order toobtain the higher dielectric constant, and such heating can have adverseeffects on the electrodes used to form the capacitor. For example, theelectrodes will often oxidize, and the oxide will act as a lowerpermittivity dielectric in series with a higher permittivity dielectric.As a result, the oxide formed from the electrode will increase theeffective distance between the electrodes, thereby decreasing thecapacitance.

Therefore, the need exists for a capacitor and method for formingcapacitors that do not suffer adverse effects when used with dielectricshaving high dielectric constants.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to a capacitor including a firstelectrode selected from a group consisting of transition metals,conductive metal-oxides, alloys thereof, and combinations thereof. Thecapacitor also includes a second electrode and a dielectric between thefirst and second electrodes. The present invention may be used to formcapacitors in integrated circuits, such as those in memory devices andprocessors.

The present invention also includes a method of forming a capacitor. Themethod includes forming a first electrode selected from a groupconsisting of transition metals, conductive metal-oxides, alloysthereof, and combinations thereof. The method also includes forming asecond electrode and forming a dielectric between the first and secondelectrodes.

The present invention solves problems experienced with the prior artbecause it provides for capacitors having improved physical structures,such as higher capacitance, smaller physical size, and smallerfootprint, by utilizing improved dielectric properties, includingelectrodes that do not form dielectrics during subsequent processingsteps. Those and other advantages and benefits of the present inventionwill become apparent from the description of the preferred embodimentshereinbelow.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

For the present invention to be clearly understood and readilypracticed, the present invention will be described in conjunction withthe following figures, wherein:

FIG. 1 is a cross-sectional view of a capacitor constructed according tothe teachings of the present invention;

FIG. 2 is a cross-sectional view of a capacitor in an early stage offabrication;

FIG. 3 is a cross-sectional view of the capacitor of FIG. 2 after thematerial forming the first electrode is removed from the top surface ofthe substrate assembly;

FIG. 4 is a cross-sectional view of the capacitor of FIG. 3 after aportion of the substrate assembly is removed from around the firstelectrode;

FIG. 5 is a cross-sectional view of the capacitor of FIG. 4 after adielectric and second conductor, including a strap, are formed;

FIG. 6 is a cross-sectional view of the capacitor of FIG. 5 after anadditional layer is formed over the capacitor;

FIG. 7 is a cross-sectional view of an alternative embodiment of acapacitor wherein the dielectric and second electrode are formed only onthe inside of the first electrode;

FIG. 8 is a cross-sectional view of the capacitor of FIG. 7 after anadditional layer and interconnect are formed;

FIG. 9 is a cross-sectional view of a post capacitor according to theteachings of the present invention;

FIG. 10 is a cross-sectional view of the capacitor including the firstelectrode, second electrode, and dielectric are formed from a non-smoothmaterial;

FIG. 11 is a cross-sectional view of the capacitor of FIG. 10 in anearly stage of fabrication after a layer of hemispherical grainpolysilicon is formed in the opening;

FIG. 12 is a cross-sectional view of the capacitor of FIG. 11 after thematerial forming the first electrode is formed;

FIG. 13 is a cross-sectional view of the capacitor of FIG. 12 after thesubstrate is partially removed and after the hemispherical grainpolysilicon is removed; and

FIG. 14 is a block diagram of a system including devices constructedaccording to the teachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

It is to be understood that the figures and descriptions of the presentinvention have been simplified to illustrate elements that are relevantfor a clear understanding of the present invention, while eliminating,for purposes of clarity, other elements. Those of ordinary skill in theart will recognize that other elements may be desirable. However,because such elements are well known in the art, and because they do notfacilitate a better understanding of the present invention, a discussionof such elements is not provided herein.

Advantages of the present invention may be realized using a number ofstructures and technologies, such as doped silicon substrate,silicon-on-insulator, silicon-on-sapphire, and thin film transistor. Theterm “substrate”, as used herein, refers to a structure that is oftenthe lowest layer of semiconductor material in a wafer or die, althoughin some technologies the substrate is not a semiconductor material. Theterm “substrate assembly”, as used herein, shall mean a substrate havingone or more layers or structures formed thereon or therein. Thesubstrate assembly may include one or more active or operable portionsof a semiconductor device.

FIG. 1 is a cross-sectional view of a capacitor 10 formed according tothe present invention. The capacitor 10 includes a first electrode 12, asecond electrode 14, and a dielectric 16 formed between the first andsecond electrodes 12, 14. The capacitor 10 is illustrated as acrown-shaped capacitor, although benefits of the present invention maybe realized with capacitors 10 having many forms, including flatcapacitors and post capacitors. The capacitor 10 may be formed on asubstrate assembly 18, and may include an interconnect 20 to, forexample, a doped region 22.

The first electrode 12 may be formed from a transition metal, such asPt, Rh, Ir, Ru, and Pd; from metals that form conductive metal oxides,such as IrO_(x), RuO_(x) and RhO_(x) (where x<4); from conductiveoxides; and from alloys of any of those materials. The first electrode12 may also be formed from any combination of the foregoing materials.The first electrode 12 may also be formed from other materials thateither do not oxidize during the formation of the capacitor 10, or whoseoxidized forms are conductive.

The second electrode 14 may be formed from any of the materials that maybe used for the first electrode 12. However, because the secondelectrode 14 is often not exposed to a high temperature processing step,the second electrode 14 may be formed from other materials that may notbe suitable for use as the first electrode 12. Examples of those othermaterials are conductive metal nitrides, WN, aluminum, TiN, TaN, andpolysilicon.

The dielectric 16 may be formed from a material that will provide a highdielectric constant, such as an insulating transition metal binary,temery, or quarternery oxide. For example, the dielectric may be formedby a chemical vapor deposition (CVD) of barium strontium titanate (BST),SrTiO₃, Sr_(w)Bi_(x)Ta_(y)O_(z), Ba_(x)Sr_(l-x)TiO₃ where 0<x<1, orTa₂O₅, followed by heating the dielectric 16 to 400 degrees C. or morein the presence of oxygen-containing ambient, such as O₂, N₂O, O₃, orNO.

The substrate assembly 18 may be formed, for example, fromborophosphosilicate glass (BPSG), TEOS oxide, SiO₂, or Si₃N₄. Theinterconnect 20 may be formed, for example, from polysilicon, TiN, ortungsten. Alternatively, the interconnect 20 may be omitted and thefirst electrode 12 may be connected directly to the doped region 22.Alternatively, the first electrode 12 may be connected to a metalcontact or metal line rather than the doped region 22, or the firstelectrode 12 may be left floating. The substrate assembly 18 may beformed from one or more layers. For example, in the illustratedembodiment a first substrate layer may be formed and planaraized. Thefirst layer may be masked and etched, and the interconnect 20 formed inthe first substrate layer. Thereafter, an additional substrate layer maybe formed above the first layer and covering the interconnect 20.

FIG. 2 is a cross-sectional view of the capacitor 10 in an early stageof fabrication. The substrate assembly 18 may be formed from a firstsubstrate layer 24 and a second substrate layer 26. The first substratelayer 24 is formed first, and the interconnect 20 may be formed in thefirst substrate layer 24 at that time. The interconnect 20 may connectthe capacitor 10 to another portion 22 of the device in which thecapacitor 10 is formed, such as a doped region. Thereafter, the secondsubstrate layer 26 may be formed on top of the first substrate layer 24,and an opening 28 may be formed in the second substrate layer 26 at thattime. The opening 28 may be formed, for example, by selectively maskingthe second substrate layer 26 so that only the portion of the secondsubstrate layer 26 where the opening 28 is to be formed is exposed, byselectively and anisotropically etching the second substrate layer 26 toform the opening 28, and then removing the mask. The first electrode 12may be formed in the opening 28 by, for example, depositing a layer ofmaterial that will form the first electrode 12, masking that layer,etching the material that is to be removed, and removing the mask toleave the first electrode 12.

FIG. 3 is a cross-sectional view of the capacitor 10 after the firstelectrode 12 has been removed from the top surface of the substrateassembly 18. The removal may be performed by, for example, a mechanicalabrasion step, such as chemical mechanical planarization (“CMP”). Inthat example, a protective material, such as photoresist, may be used tofill the opening 28 to prevent materials removed by the CMP from fallinginto the opening 28. Alternatively, the removal can be performed by ablanket etch back process.

FIG. 4 is a cross-sectional view of the capacitor 10 after a portion ofthe substrate assembly 18 has been removed to expose vertical portionsof the first electrode 12. The substrate assembly 18 may be removed by,for example, an etch that is selective to the substrate assembly 18 butwhich does not etch the first electrode 12. The substrate assembly 18may be etched so that the first electrode 12 remains partially recessedin the substrate assembly 18, thereby providing structural stability tothe capacitor 10.

FIG. 5 is a cross-sectional view of the capacitor 10 after thedielectric 16 and a second electrode 14 have been formed over the firstelectrode 12, thereby completing the capacitor 10. The dielectric 16 maybe formed, for example, by forming a layer of the dielectric 16 on theentire surface, and then selectively removing the dielectric 16 so thatit remains only where desired. In particular, the dielectric 16 may bedeposited over the entire surface by sputtering or CVD. The dielectric16 on the first electrode 12 may be masked, such as with photoresist,and the exposed dielectric may be removed with a selective etch.Alternatively, the insulating dielectric 16 need not be removed at all.The second electrode 14 may be formed after the dielectric 16 and in amanner similar to that used to form the dielectric 16. In contrast tothe embodiment illustrated in FIG. 1, the capacitor 10 may include aportion 30 of the second electrode 14, known as a strap 30, formed as acontact for connecting the second electrode 14 to another portion of thedevice in which the capacitor 10 is formed. Similarly, another portion32 of the second electrode 14 may connect to other capacitors so as totie several second electrodes together at a common potential, such asground.

FIG. 6 is a cross-sectional view of the capacitor 10 after an additionallayer 40 is formed over the capacitor 10. The additional layer 40 may beused to separate the capacitor 10 from whatever may be formed above thecapacitor 10. The additional layer 40 may be formed, for example, by aCVD process and from the same materials used to form lower layers of thesubstrate assembly 18. The additional layer 40 may be planarized, suchas by CMP, and an interconnect 42 may be formed in the additional layer40 to connect the second electrode 14, via the strap 30, to anotherportion of the device in which the capacitor 10 is formed.

FIG. 7 is a cross-sectional view of an alternative embodiment of thecapacitor 10 in which the dielectric 16 and the second electrode 14 areformed only within the first electrode 12. In that embodiment, thesubstrate assembly 18 may not be etched as described hereinabove withrespect to FIG. 4. The dielectric 16 and second electrode 14 may beformed in a manner similar to the first electrode 12, such as by CVDfollowed by mechanical abrasion to remove unwanted material from the topsurface of the substrate assembly 18.

FIG. 8 is a cross-sectional view of the capacitor 10 illustrated in FIG.7 after an additional layer 40 has been formed and after an interconnect42 has been formed connecting the second electrode 14 to another portionof the device in which the capacitor 10 is formed. In the illustratedembodiment, the interconnect 42 is connected to the second electrode 14without the use of the strap 30 (illustrated in FIGS. 5 and 6).

FIG. 9 is a cross-sectional view of an alternative embodiment of thepresent invention formed as a post capacitor 10. That embodimentincludes the first electrode 12, the second electrode 14, and thedielectric 16 formed on a post 50. The post 50 may be formed, forexample, by forming a temporary layer on the substrate assembly 18,forming an opening in the temporary layer, filling the opening with amaterial to form the post 50, and removing the temporary layer to leavethe post 50. The post 50 may be formed, for example, from polysilicon.

FIG. 10 is a cross-sectional view of an alternative embodiment of thepresent invention wherein the first and second electrodes 12, 14 and thedielectric 16 have a non-smooth surface. The non-smooth surfacesincreases the surface area of the first and second electrodes 12, 14 andthe dielectric 16, thereby increasing the capacitance of the capacitor10. The capacitor 10 may be formed, for example, by using a non-smoothmold, such as hemispherical grain (HSG) polysilicon, on which the firstelectrode 12 may be formed. Such a process results in the firstelectrode 12 having an inverted hemispherical grain on the side formedon the HSG polysilicon (that is the outside in the illustratedembodiment), and an inverted hemispherical grain on the side oppositethat formed on the HSG polysilicon (that is the inside in theillustrated embodiment). Thereafter, the mold may be removed and thedielectric 16 and second electrode 14 may be formed over the firstelectrode 12, conforming to its non-smooth surface and assuming asimilar non-smooth surface. The dielectric 16 and the second electrode14 formed by that process have hemispherical grain on one side andinverted hemispherical grain on another side, in a manner analogous tothe first electrode 12. It is desirable that the first electrode 12 beset into a recess, such as a recessed interconnect 20, so as to providestructural stability to the first electrode 12.

FIG. 11 is a cross-sectional view of the capacitor 10 illustrated inFIG. 10 in an early stage of fabrication wherein a layer of HSGpolysilicon 60 is formed in the opening 28 and on the top surface of thesubstrate assembly 18. The layer of HSG polysilicon 60 may be formed,for example, with a CVD process. The interconnect 20 is recessed belowthe bottom surface of the opening 26.

FIG. 12 is a cross-sectional view of the capacitor 10 after a conductivelayer that will form the first electrode 12 is formed over the HSGpolysilicon 60. HSG polysilicon has a course, grainy surface, and whenthe layer that will form the first electrode 12 is formed on the HSGpolysilicon 60, that layer conforms to the HSG polysilicon 60 andassumes a similar, non-smooth surface. The non-smooth surface of the HSGpolysilicon has a surface area that is between about 150% and about 200%greater than the surface area of smooth polysilicon. It is desirable toetch the HSG polysilicon 60 from the recessed interconnect 20 before thelayer that will form the first electrode 12 is formed, as is done in theillustrated embodiment. As a result, the first electrode 12 will be indirect contact with the interconnect 20. Otherwise, if the HSGpolysilicon 60 is between the first conductor 12 and the interconnect20, it may oxidize and increase the resistance of between theinterconnect 20 and the first electrode 12. Furthermore, if HSGpolysilicon 60 is supporting the first electrode 12, the first electrode12 may be damaged or destroyed when the HSG polysilicon 60 in removed ina subsequent fabrication step.

FIG. 13 is a cross-sectional view of the capacitor 10 after thesubstrate assembly 18 is partially removed and the HSG polysilicon 60 isremoved. The partial removal of the substrate assembly 18 exposes theHSG polysilicon 60, which may then be removed with a selective etch,such as tetra methyl ammonium hydroxide, leaving the first electrode 12.Thereafter, the dielectric 16 and the second electrode 14 may be formedto result in the capacitor illustrated in FIG. 10. The dielectric 16 andsecond electrode 14, when formed over the first electrode 12, will alsohave a grainy surface, thereby increasing their surface areas.

FIG. 14 is a high level block diagram illustrating a system 61 includinga first device 62, a bus 64, and a second device 66. The system 61 maybe, for example, a memory system or a computer system. The first device62 may be a processor, and the second device 66 may be a memory. Thefirst device 62 and the second device 66 may communicate via the bus 64.The first and second devices 62, 66 may include capacitors 10,constructed according to the teaching of the present invention.

The present invention also includes a method of forming structures anddevices, such as capacitors. The method includes forming a firstelectrode selected from a group consisting of transition metals,conductive metal-oxides, and alloys thereof. The method also includesforming a second electrode and forming a dielectric between the firstand second electrodes. The method includes many variations, as describedin the teachings hereinabove.

Those of ordinary skill in the art will recognize that manymodifications and variations of the present invention may beimplemented. For example, one of the interconnects 22, 42 may be omittedand the corresponding conductor may be left to “float”. The foregoingdescription and the following claims are intended to cover all suchmodifications and variations.

1-80. (canceled)
 81. A method, comprising: forming a substrate assembly; forming a first electrode on the substrate assembly, wherein the first electrode is formed to include at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof; forming a dielectric on the first electrode and an uppermost surface of the substrate assembly; and forming a second electrode on the dielectric, wherein the second electrode is formed to include at least one non-smooth surface, and wherein the dielectric and the second electrode are formed only within the first electrode.
 82. The method of claim 81, wherein forming the substrate assembly includes forming a first substrate layer before forming the first electrode.
 83. The method of claim 81, wherein forming a first substrate layer further includes planarizing the deposited material.
 84. The method of claim 81, wherein the method futher comprises forming an additional substrate layer after forming the second electrode.
 85. The method of claim 84, wherein forming the additional substrate layer includes: planarizing the additional layer; and forming an interconnect in the additional layer.
 86. The method of claim 85, wherein planarizing the additional layer includes planarizing the additional layer by chemical mechanical polishing.
 87. The method of claim 85, wherein forming the interconnect includes forming the interconnect on the second electrode.
 88. The method of claim 87, wherein forming the interconnect on the second electrode includes forming the interconnect on a strap of the second electrode.
 89. The method of claim 81, wherein forming the first electrode includes forming the first electrode on an interconnect.
 90. The method of claim 81, wherein forming the first electrode includes depositing a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the substrate assembly.
 91. The method of claim 90, wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof includes depositing a transition metal selected from the group consisting of Pt, Rh, Ir, Ru, and Pd.
 92. The method of claim 90, wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof includes depositing a conductive oxide selected from the group consisting of IrO_(x), RuO_(x), and RhO_(x,) wherein x<4.
 93. The method of claim 81, wherein forning the dielectric includes depositing an insulating metal oxide on the first electrode.
 94. The method of claim 93, wherein depositing the insulating metal oxide includes depositing a material selected from the group consisting of barium strontium titanate, SrTiO₃, Sr_(w)Bi_(x)Ta_(y)O_(z), BaxSr_(l-x)TiO₃, where 0<x<1, and Ta₂O₅.
 95. The method of claim 93, wherein forming the dielectric further comprises heating the insulating metal oxide in the presence of an oxygen-containing ambient.
 96. The method of claim 81, wherein forming the second electrode includes depositing a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the dielectric.
 97. The method of claim 96, wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the dielectric includes depositing a transition metal selected from the group consisting of Pt, Rh, Ir, Ru, and Pd on the dielectric.
 98. The method of claim 96, wherein depositing the material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof on the dielectric includes depositing a conductive oxide selected from the group consisting of IrO_(x), RuO_(x), and RhO_(x,) wherein x<4.
 99. The method of claim 81, wherein forming the second electrode includes depositing a material selected from the group consisting of conductive metal nitrides, aluminum, and polysilicon on the dielectric.
 100. The method of claim 99, wherein depositing the material on the dielectric includes depositing a conductive metal nitride selected from the group comprising WN, TiN, and TaN on the dielectric.
 101. The method of claim 81, wherein forming the second electrode includes forming a strap. 